Embedded 2T_pFlash memories are usually integrated into a system-on-chip, such as a subscriber identity module (SIM) card chip of a mobile phone or a smart bankcard chip, in form of an intellectual property (IP). Because of this feature, they are called “embedded” to distinguish from products of stand-along flash memories.
A single memory unit is formed by connecting two P-type metal-oxide-semiconductor (MOS) field transistors (a select gate transistor and a control gate transistor) in series, so it is called 2T_pFlash. The PMOS transistor is an elementary device for the modern very large scale integrated circuit. The PMOS transistor has four control terminals including a gate terminal, a drain terminal, a source terminal and a bulk terminal. The transistor can be turned on or off (corresponding to current on or off) by controlling the voltages applied to the four terminals. The select gate transistor is typically connected in series with the control gate transistor to form a “2T flash memory unit”. A flash memory unit with a specific address can be selected or deselected to operate through the select gate transistor. The control gate transistor is a unit storing “0/1” in the common sense. Specific operations are performed to make the transistor to present different electric characteristics (e.g., different threshold voltages), so as to represent “0” or “1”. The floating gate is usually embedded between the control gate and the silicon substrate of the control gate transistor to form a sandwich structure. The floating gate and the control gate are insulated by an oxide-nitride-oxide insulating film disposed therebetween, and the floating gate and the silicon substrate are insulated by an oxide insulating film. The floating gate itself is usually N-type or P-type doped polysilicon, which can be used to store charges to change the electric characteristics of the control gate PMOS transistor.
The embedded 2T pMOS flash memory array uses a NOR structure (as shown in FIG. 1), so as to ensure random access. A bit line (which is usually referred to as “BL” for short) in FIG. 1 is used to control a voltage of a drain of a transistor. A word line (which is usually referred to as “WL” for short) is used to control a voltage of a gate of the transistor. A source line (which is usually referred to as “SL” for short) is used to control a voltage of a source of the transistor. In the NOR structure, any one of the flash memory units can be read by applied different bias voltages to the BL/WL/SL lines. Taking the memory unit marked by a circuit shown in FIG. 1 as an example, the line SG-1 is used to turn on the select gate PMOS transistor, a suitable gate voltage is applied to the control gate PMOS transistor through the WL-1, and then “0”/“1” is determined based on whether there is a current between the BL-1 and the SL-1 during a read operation.
The conventional 2T_pFlash device structure and array structure can achieve a minimum power of 150 uA/Mhz and a minimum read time of 30 ns, which needs further improvement.